The memory used by microprocessors or microcontrollers generally comprises a plurality of memory locations, wherein each location may be used for storing data. For read or write access to a memory location, the microprocessor generates an address corresponding to the memory location and sends it over the address bus connecting the microprocessor to the memory. Consequently, a memory address should be composed of a sufficient number of bits for uniquely identifying each memory location accessible by the microprocessor. For example, a 64-kilobyte memory would require a 16-bit address for each memory location in the memory to be uniquely identified.
As the size of memories tend to increase at a constant cost, there is a need for increasing the size of the addressable space accessible by the microprocessor. For this purpose, the microprocessor should be provided with an address bus having the corresponding number of lines, which unavoidably leads to an increase in the microprocessor's complexity both in its structure and in its command register.
For increasing the microprocessor's addressable space without substantially enlarging its structure, it has already been suggested to integrate a page or segment register within the microprocessor's processing unit for storing the additional most significant bits. These bits are concatenated (i.e., linked together) with the addresses generated by the processing performed by the microprocessor.
However, for this approach to be implemented, additional commands have to be added to the microprocessor's command register to manage the page or segment register. In addition, this approach leads to a division of the space addressable by the microprocessor into relatively isolated blocks and introduces additional constraints in the compilers.
Another approach includes using indexes which are added to the addresses manipulated by the processing unit of the microprocessor. This results in a rather heavy additional processing for only a slight increase in the addressable space.